The present invention relates generally to the field of graphics processing; more particularly, to methods and apparatus directed to efficiently loading and accessing data in a graphics processing system.
A requirement of a modern computer graphics processing system is that it be capable of manipulating and performing calculations on huge quantities of data at very fast speeds. This has led researchers to search for better techniques for handling and storing data to be output to a display device in real-time.
The demand for more efficient methods and circuits for dealing with graphics data continues to grow rapidly. The increased use of techniques for three-dimensional texturing (solid texturing), modeling, and shading in computer graphics and animation has fueled this demand. For example, it is now possible for three-dimensional objects and shapes created on a personal computer or workstation to be filled in with textures simulating natural materials and natural phenomena. Realistic images having textures resembling marble, wood, or stone are now commonly displayed. Likewise, computer researchers and scientists have successfully simulated natural phenomena such as fog, waves, fire, and clouds for display on a computer screen.
A xe2x80x9ctexturexe2x80x9dxe2x80x94sometimes referred to as a xe2x80x9cpatternxe2x80x9d or xe2x80x9cwallpaperxe2x80x9dxe2x80x94is simply an image that is used as surface covering for objects or shapes created by a graphics program running on a computer. Textures come in many varieties. Examples include bump mapping, which simulate the appearance of surface bumps without actually modifying the geometry of the object; light maps which give the appearance of smooth diffuse lighting; displacement mapping, in which textures are used actually to move the surface; and solid textures that give consistent textures of all surfaces of an object regardless of distortions of the surface parameter space.
A texture may be explicitly specified by storing all the complex details of the scene or sequence in a bit-map that contains the value of each pixel (called a xe2x80x9ctexelxe2x80x99 when referring to texture data) in the image. This obviously requires a large amount of storage space within the computer as well as an advanced graphics processing subsystem. Typically, the processor of a computer graphics subsystem loads the texture data into memory before is used by the graphics application. Since the end-user must wait for the texture data to be completely loaded into memory before starting the application (e.g., playing a video game), it is desirable to reduce this time as much as possible.
One architectural technique for increasing the memory access speed of graphics data is a xe2x80x9ctiledxe2x80x9d memory organization. In a tiled memory, the memory mapped for the display screen is translated into tiles within the memory (e.g., DRAM) in a way that permits fast access of neighboring pixels in the array. By way of example, U.S. Pat. No. 5,736,988 teaches an apparatus and method for storing graphics data as a collection of individual addressable tiles for fast retrieval in a computer system. As further background, U.S. Pat. Nos. 5,877,780 and 5,781,200 both disclose a tiled memory architecture for storing graphics data. The memory mapping taught involves a translation between a received linear address (representing a screen pixel location and color) to a physical address stored in within the DRAM.
U.S. Pat. No. 5,828,382 of Wilde describes a graphics subsystem that includes graphics hardware for permitting graphics texture maps to be dynamically cached internally within the graphics hardware. Textures are stored in system memory in a tile format that allows an entire cache tile to be stored linearly in memory space. According to Wilde, storing the textures in a tiled linear format allows the graphics processor to fetch the tile across the peripheral component interface (PCI) bus in a single burst cycle.
Other examples of the use of a tiled memory organization for storing display images include U.S. Pat. No. 5,815,168, which discloses a display controller for receiving and storing display data in memory in a tiled addressing format. U.S. Pat. No. 5,675,826 discloses a plurality of tiled memories in which data stored in the tiled memories is offset relative to each other by a delay unit upon writing of the data into the memory units. U.S. Pat. No. 5,263,136 discloses an image memory management system for tiled images.
Despite the widespread use of tiled memories and improved processor performance, there is still a need for a solution to the problem of how to achieve fast loading of texture data in a computer graphics system.
The present invention comprises as apparatus for loading texture data into a tiled memory. In one embodiment the apparatus comprises state machine logic to generate a sequence of addresses for writing a cacheline of texture data into the tiled memory according to Y-major tiling. The cacheline comprises quadwords (QWs) 0-3, wherein the sequence corresponds to an ordering of the QWs 0-3. The ordering consisting of either: (a) QW0, QW1, QW2, QW3; (b) QW1, QW0, QW3, QW2; (c) QW2, QW3, QW0, QW1; or (d) QW3, QW2, QW1, QW0, depending upon a starting address.